An increasingly important design paradigm in
integrated circuit design is that of Field-Programmable Gate Arrays
(FPGAs). The significance of FPGAs architectures is primarily due to the
inherently shorter turnaround time and the lower cost as compared to
ASIC designs. Therefore, there is a continual demand for smaller,
faster, and low-power FPGAs. Technology scaling supports the development
of new FPGA devices satisfying these requirements. A number of
challenges has, however, to be satisfied such that high-performance
miniaturized FPGAs can be delivered.
This research proposal intends to address the growing in importance
reliability issues for high-performance and complex FPGAs. Consequently,
the objective of this proposal is to provide efficient means such that
the expected performance of the FPGAs is guaranteed throughout the
lifetime of a device. These means will include both the exploration of
redundancy techniques and the development of design tools during design
and/or real-time that will ensure a specified level of reliability. To
date fault masking in commercial FPGAs is merely mitigated by costly
redundancy techniques (Xilinx Triple Modular Redundancy), whereas
reliability issues usually impose hardware redesign. |
